User talk:Cloudream

Your edit of RDNA (microarchitecture)

Hi, I have spotted your [edit] and wanted to ask you a few questions. Did you notice that density numbers from the article you referenced contradict not only numbers AMD reported in print about Navi 31, but also what is known about the density of TSMC's N5 and N6 processes in general? And in case you did notice that, why do you believe these numbers are the correct ones (or at least more correct than what AMD said in print) – since you did not just add a contradicting source, but deleted density numbers from AMD's official document along with the reference? 188.66.35.198 (talk) 20:48, 16 November 2022 (UTC)[reply]

About "numbers AMD reported in print about Navi 31", in that footprint AMD clearly said it is the density of the "work group processor (compute unit pair)" of RDNA3/2, not the chip(let) density.

For MCM, the old density (109m/mm²) was unlikely to be correct as it is almost the theoretical peak density of N6, which is possible for a pure logic chip, but not for I/O&SRAM chip, the new density (55.4m/mm²) was from the new reference directly and align with other mass-produced N6 chips.

For GCD, the new density (149.3m/mm²) was calculated with reported transistor count and 306mm², this size was from AMD's RDNA3 launch news, it is more precise than the 300mm² used by tom's hardware and AMD's slides, both 300 and 306 are from AMD so either could be the correct. Cloudream (talk) 12:34, 17 November 2022 (UTC)[reply]

Please check https://en.m.wikipedia.org/wiki/Talk:RDNA_(microarchitecture)#152.3_Mtr.%2Fmm²_for_Navi_31_claimed_by_Tom's_Hardware_looks_fishy_as_well for my reply, this discussion is better held on the article's talk page. — Preceding unsigned comment added by 188.66.33.43 (talk) 21:17, 18 November 2022 (UTC)[reply]