User:Mpelcat

PREESM

PREESM 0.5.0 screenshot
Developer(s)	PREESM Development Team at IETR
Initial release	2008
Written in	Java as Eclipse plug-ins
Type	Rapid Prototyping Tool
License	CeCILL-B or CeCILL-C depending on the plug-ins
Website	sourceforge.net/projects/preesm/

PREESM (the Parallel and Real-time Embedded Executives Scheduling Method) is an open source rapid prototyping and code generation tool. It is primarily employed to simulate signal processing applications and generate code for multi-core Digital Signal Processors. PREESM is developed at the Institute of Electronics and Telecommunications-Rennes (IETR) in collaboration with Texas Instruments France in Nice.

The PREESM tool inputs are an algorithm graph, an architecture graph, and a scenario which is a set of parameters and constraints that specify the conditions under which the deployment will run. The chosen type of algorithm graph is a hierarchical extension of Synchronous Dataflow (SDF) graphs named Interface-Based hierarchical Synchronous Dataflow (IBSDF). The architecture graph is named System-Level Architecture Model (S-LAM). From these inputs, PREESM maps and schedules automatically the code over the multiple processing elements and generates multi-core code.

Documentation

Online documentation is provided in the PREESM SourceForge MediaWiki. Installation and use are explained in Flash Tutorials.

Publications

• Pelcat, Maxime; Piat, Jonathan; Wipliez, Matthieu; Aridhi, Slaheddine; Nezan, Jean-François (2009). "An Open Framework for Rapid Prototyping of Signal Processing Applications". EURASIP Journal on Embedded Systems. {{cite journal}}: External link in |journal= and |title= (help)

• Pelcat, Maxime; Nezan, Jean-François; Piat, Jonathan; Croizer, Jérôme; Aridhi, Slaheddine (2009). "A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems". DASIP Sophia Antipolis. {{cite journal}}: External link in |title= (help)

• Piat, Jonathan; Bhattacharyya, Shuvra S.; Pelcat, Maxime; Raulet, Mickaël (2009). "Multi-Core Code Generation From Interface Based Hierarchy". DASIP Sophia Antipolis. {{cite journal}}: External link in |title= (help)

• Piat, Jonathan; Bhattacharyya, Shuvra S.; Raulet, Mickaël (2009). "Interface-based hierarchy for synchronous data-flow graphs". SiPS Tampere. {{cite journal}}: External link in |title= (help)

• Pelcat, Maxime; Menuet, Pierrick; Aridhi, Slaheddine; Nezan, Jean-François (2009). "Scalable compile-time scheduler for multi-core architectures". DATE Nice. {{cite journal}}: External link in |title= (help)