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Template:AMD Turion II Neo (Geneva, dual-core)

From Wikipedia, the free encyclopedia
Model number Clock
speed
L2 cache FPU width[1] Hyper
Transport
Multi TDP Socket Release date Part number
Turion II Neo N40L 1.5 GHz 2 × 1 MB 128-bit 1.6 GHz 7.5× 15 W Socket ASB2 April 26, 2010 TEN40LGAV23GME
Turion II K625 1.5 GHz 2 × 1 MB 128-bit 1.6 GHz 7.5× 15 W Socket ASB2 May 12, 2010 TMK625GAV23GM
Turion II K645 1.6 GHz 2 × 1 MB 128-bit 1.6 GHz 15 W Socket ASB2 January 4, 2011 TMK645GAV23GM
Turion II K665 1.7 GHz 2 × 1 MB 128-bit 1.6 GHz 8.5× 15 W Socket ASB2 May 12, 2010 TMK665GAV23GM
Turion II K685 1.8 GHz 2 × 1 MB 128-bit 1.6 GHz 15 W Socket ASB2 January 4, 2011 TMK685GAV23GM
Turion II Neo N54L 2.2 GHz 2 × 1 MB 128-bit 1.6 GHz 11× 25 W Socket ASB2 May 2010 TEN54LSDV23GME

References

  1. ^ "The 2010 AMD Mainstream Platform". Amd.com. Retrieved 2014-04-30.