Template:AMD CDNA Products
| Model (Code name) |
Released | Architecture & fab |
Transistors & die size |
Core | Fillrate[a] | Processing power (TFLOPS) | Memory | TBP | Software interface |
Physical interface | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Vector[a][b] | Matrix[a][b] | |||||||||||||||||||||
| Config[c] | Clock[a] (MHz) |
Texture[d] (GT/s) |
Pixel[e] (GP/s) |
Half (FP16) |
Single (FP32) |
Double (FP64) |
INT8 | BF16 | FP16 | FP32 | FP64 | Bus type & width |
Size (GB) |
Clock (MT/s) |
Bandwidth (GB/s) | |||||||
| AMD Instinct MI100 (Arcturus)[1][2] |
Nov 16, 2020 | CDNA TSMC N7 |
25.6×109 750 mm2 |
7680:480:- 120 CU |
1000 1502 |
480 720.96 |
- | 15.72 23.10 |
7.86 11.5 |
122.88 184.57 |
61.44 92.28 |
122.88 184.57 |
30.72 46.14 |
15.36 23.07 |
HBM2 4096-bit |
32 | 2400 | 1228 | 300 W | PCIe 4.0 ×16 |
PCIe ×16 | |
- ^ a b c d Boost values (if available) are stated below the base value in italic.
- ^ a b Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- ^ Unified shaders : Texture mapping units : Render output units and Compute units (CU)
- ^ Texture fillrate is calculated as the number of texture mapping units multiplied by the base (or boost) core clock speed.
- ^ Pixel fillrate is calculated as the number of render output units multiplied by the base (or boost) core clock speed.
Template documentation | You can . |
 | Common place to discuss layout and style of the AMD GPU tables at: Talk:List of AMD graphics processing units. |
References
- ^ "AMD Instinct MI100 Brochure" (PDF). AMD. Retrieved December 25, 2022.
- ^ "AMD CDNA Whitepaper" (PDF). AMD. Retrieved December 25, 2022.