Talk:Physical Address Extension/Archives/2015/February

History section - AMD's changes

Seriously, who said "It was extended[when?] by AMD to add a level to the page table hierarchy, to allow it to handle up to 52-bit physical addresses"? Is it said by Jeh? why? Make a further explanation! OK, Jeh, or anyone else, never leave any notes to my own talk page! Janagewen (talk) 02:27, 18 November 2014 (UTC)

That's a good catch! It isn't true. I don't think I wrote that, but it doesn't matter who wrote it; it's wrong. (Wikipedia wants to focus on fixing things, not on assigning blame.)

The additional level of page table hierarchy is necessary to allow it to handle wider virtual addresses, not physical.

What did happen was that when AMD defined that four-level page table structure for x64, they also spec'd that they were widening the PFN field in the page table, etc., entries... thus allowing more than 36 bits of physical address to come out of the translation. But they didn't make the entries wider. They were already 64 bits wide under 32-bit PAE. The PFN was in bits 12 through 35, bits 36 through 62 were unused. AMD just extended the PFN field to include bits 12 through 51. (Bits 52 through 62 are reserved for the OS, and bit 63 is the NX bit.) This by the way also works on x64 processors when the processor is in 32-bit mode.

Also, NX bit functionality was already there long before AMD started working on x64. So the claim that AMD added NX at this time is wrong too. 32-bit PAE already supported NX.

I can't see why this is related to 64-bit virtual address translation (which is what necessitated the four-level tables) at all.

I don't have time to fix it myself right now, not and have it properly referenced. But I don't have to be the one to fix it.

Aside: You know, a much shorter section head would leave a lot more room for a meaningful edit summary. Jeh (talk) 03:15, 18 November 2014 (UTC)

Sorry! Janagewen (talk) 03:55, 18 November 2014 (UTC)

Not a big or even medium deal, just thought I'd mention it. Thank you again for the "catch." Jeh (talk) 04:25, 18 November 2014 (UTC)

ok, it's fixed. Jeh (talk) 02:46, 30 December 2014 (UTC)

Aside: The original phrasing was ok, depending on how you interpret the first comma:

"It was extended by AMD to add a level to the page table hierarchy, to allow it to handle up to 52-bit physical addresses, add NX bit functionality, and make it the mandatory memory paging model in long mode."

If you assume that this means that adding a level to the page table hierarchy was done to allow handling of 52-bit PAs, that's incorrect. But if you regard this as describing four independent changes, i.e. "adding a level to the page table hierarchy" and "to allow it to handle up to 52-bit physical addresses" are separate steps with the second not depending on the first, then that correctly describes the changes AMD made. As I noted previously, the additional "level" was added to support wider virtual addresses... but that does not mean that AMD did not also extend the PFN field to support up to 52-bit physical addresses.

Further aside to Janagewen or whatever IP or nick you show up with next: I went through the page history. I did not write the text in question. I'm not going to give a diff to identify who did write it (or when) because, as I said above, what we do here on WP is identify and fix errors, not try to call out those who made them. (But if you really care, you can find it just as I did.) Depending on interpretation this wasn't even an error, just phrasing that could be misinterpreted. Nevertheless, thanks for calling attention to it so that it could be improved. Jeh (talk) 19:19, 30 December 2014 (UTC)

Es ist schade, a nonsense explanation. Najagewinnen (talk) 00:47, 5 February 2015 (UTC)

Can you explain exactly how you think it is nonsense? 'cause I'm not seeing it. Perhaps someone else will be able to offer their evaluation of the original text, and/or of my explanation above, and/or of the clarified text in the article (an edit that was made in response to Janagewen's message above).

In any case, the article text was clarified some time ago.

Your removal of the clarified text was unjustified as it a) describes something that did happen in PAE's "History" (the section title) and b) explains what "This" refers to in the sentence that follows, "This version of PAE...". I have therefore restored the sentence. Jeh (talk) 02:42, 5 February 2015 (UTC)

OK, let me explain it for you. The removal text is nonsense, because PAE is a optional feature for IA-32 architecture, and AMD64 is another architecture, not IA-32, put it as one integrated component rather than a feature. And the references somebody made does really seem nonsense, and tends to mislead. For your response to question of this section, I've seen nothing useful or meaningful at all, and obviously failed to explain it, so I said it non-sense. I am a computer architecture learner getting touch with x86 architecture for more than 12 years. So I am very sorry, your explanation is nonsense. Najagewinnen (talk) 08:29, 5 February 2015 (UTC)

The AMD64 (or x64, or x86-64, whatever) architecture is not regarded as "another" architecture, independent of and separate from x86. Rather, x64 includes all of x86 as a subset. That's why you can boot a 32-bit x86 OS on an AMD 64-bit processor and run 32-bit apps and device drivers and it all "just works", completely binary compatible.

When AMD defined x64, they included PAE. They started with the x86 version of PAE, and extended it, as is described in the article. Just as they started with everything else that was in x86, and extended it. (More and wider registers, etc.) AMD's documentation for x64 states clearly that these processors boot into 32-bit, x86-compatible mode - called "legacy mode"; that PAE, just as it is defined for 32-bit-only x86 processors, is available in legacy mode; that PAE must be enabled before switching to long mode (64-bit mode), and that PAE must remain enabled while in long mode. So PAE on x64 is not some sort of very different thing, defined independently of x86. It is PAE as it was on x86, but with a fourth level added to the page table hierarchy.

The fact that PAE was a late-added feature to x86, but was defined from the start as being part of x64 (and not optional - you can't turn off the PAE bit while in long mode, or the machine will GPF), is irrelevant.

The reference given (page 120 of the AMD64 Architecture Programmer’s Manual, Volume 2: System Programming) is absolutely clear on this, and not "misleading". Just because you disagree with it doesn't mean it's misleading. Maybe you just don't understand it yet.

Please note also this from page 437, same book: "Long mode requires the use of physical-address extensions (PAE) in order to support physical-address sizes greater than 32 bits." You can't just deny that by claiming "that's nonsense." AMD is using the term "PAE" to include the addressing mode that's used while in long mode, not just the x86 form of PAE. And Wikipedia must follow its sources.

However, you have called my attention to the lede sentence, which I will now fix. Jeh (talk) 10:38, 5 February 2015 (UTC)

I have to declare that I am not Janagewen, in order not to be reported by Jeh and blocked. But for Jeh's viewpoint above, I should have to say it is not 100 percent correct. Let the people from AMD or Intel further explain this question. Let this discussion stay! Starvisionstar (talk) 05:55, 7 February 2015 (UTC)

Some a person whose IP from China mainland reported me as sock puppet of Janagewen. But the question to me is that how could he or she prove that he or she is Chinese? The can I call it nationality puppet? OK, that does not matter. The matter is that, PAE is short for Physical Addressing Extension, pay attention to the word Extension! Under AMD64 or x64 architecture, the bit width of linear address is 64-bit (48-bit implemented), so there is no needing to extend physical addressing at all! So talking about PAE for Long mode or IA-32e mode is meaningless and a bit mislead. Frankly and obviously, AMD64 is paging only architecture, so paging is enabled without needing mentioned at all. And Physical Addressing Extension is a processor feature not architecture feature. Who is confused, who is not confused? I just clear this very fact but being attack by so many and many strange people. Do please leave a person a bit drop of respect, ok? At least, I paid 4 years on computer science in college, I tried to dip into the real computers to inspect the actual bit width supported by each kind of physical processors to re-arrange that stupid x86 table. What all I done here is not disruptive edits at all! Starvisionstar (talk) 11:56, 7 February 2015 (UTC)

If people continue using IP sock puppet to block me, I wish your Wikipedia.org should block or lock all the IP address I could reach into, not let me waste time contribute at all. Starvisionstar (talk) 12:00, 7 February 2015 (UTC)

If you (or someone you know) has a complaint about WP:SPI and subsequent actions, here is not the place to discuss it. Jeh (talk) 22:35, 7 February 2015 (UTC)

Paging in x64 long mode is most certainly not "enabled without needing mentioned [sic] at all". There is a "paging enable" bit in CR0 (CR0.PG) in long mode just as there is in compatibility mode. It must be set before entering long mode, and it must remain set while in long mode.

Make no mistake: I see what you mean about the name "physical address extension". If one considers long mode only, the page table structure there is not an extension to anything, since there is no other option in long mode. But one cannot consider long mode only. The page table structure in long mode is quite obviously an "extended" (to four levels, 48 bits of v.a., and 52 bits of p.a.) version of PAE in what is now called compatibility mode. More to the point, a primary source (the AMD documentation) calls it "PAE". The bit that enables it is still called CR4.PAE.

However, I do find support for your position in the analagous Intel documentation. It does not use the term "PAE" when referring to address translation in long mode. They refer to it as "IA-32e paging". Still, CR0.PG and CR4.PAE must be set before entering long mode, and must remain set while in long mode. Jeh (talk) 22:48, 7 February 2015 (UTC)

So you are misleading our innocent readers again! Jeh, I persude you not to report but read more and more before your contribution. Starvisionstar (talk) 22:55, 7 February 2015 (UTC)　

Hm. Accusation of "misleading" is exactly what Janagewen used to do. Aside from that, "misleading" would imply that I knew something else in advance. Tell me, had you read the Intel64 documentation previously? If yes, why didn't you point to it? Instead, I went and found information that gives support to your point of view, and instead of just not mentioning it (which would indeed have been "misleading") I go right ahead, reference it, and put it in the article. And you accuse me of "misleading"? On the contrary, I have been completely open in my process here. You are falsely accusing me of lying, sir. Jeh (talk) 23:12, 7 February 2015 (UTC)

I just said you are misleading, but not lying. I dislike you because you always try to block me out of Wikipedia.org. Since the very day I met you on Wikipedia.org, I think you are making advertisements of AMD64 all the time. I should have respected you all the time, but what you done to my user account I lose my faith. PAE is a processor feature, invisible to the architecture, MMU exactly, something like a FPU, I mean external to the CPU core and associated architecture. AMD64 is a paging only architecture, paging is the only way to address physical resources. 48-bit virtual address to 36 to 48-bit physical address without needing extending at all. So the to enable PAE before jumping into Long Mode is only a way by form or tradition. PAE is a word talking about the world for 32-bit computing, as to 64-bit world, only physical addressing could reach out more than 64-bit is essentially meaningful. I come here just want to correct the misleading contents and discuss useful things. Wikipedia.org is for everyone, isn't it? And I am only one of everyone, so why always keep me out of here. Starvisionstar (talk) 23:23, 7 February 2015 (UTC)

See, Janagewen, this is one of the problems with your "contributions": You don't express yourself well. When you originally brought this up, you did not make at all clear what your complaint was. I originally thought it was about the change to "52-bit physical addresses" - that change could have been accomplished within the x86 PAE structure. And when I replied to that effect, and fixed the article accordingly, it was still some time before you told us that that wasn't what you were talking about? Apparently you don't read people's replies to you? Why did it take months for you to describe what you were really on about?

"Advertisements of AMD64"? Um, AMD invented the 64-bit extensions to 32-bit x86, so their documentation is necessarily going to be quoted. (And as they inventor of the technology, they get to pick names for parts of it, whether you think they're "misleading" or not.) If you think that that is an "advertisement", then you do not well understand the meaning of that word.

"PAE is a processor feature, invisible to the architecture, MMU exactly, something like a FPU, I mean external to the CPU core and associated architecture." This is just your interpretation of things; I find no support for these claims. "PAE is invisible to the architecture"??? What? It's defined in the architecture manuals!

"AMD64 is a paging only architecture". No. An AMD64 processor can run in real mode if you want it to. Remember, AMD64 includes all of 32-bit x86.

"So the to enable PAE before jumping into Long Mode is only a way by form or tradition." No, it's required because otherwise it would be much more difficult to set up the required page tables just before the transition to long mode.

"PAE is a word talking about the world for 32-bit computing"... not according to the AMD docs. Wikipedia must follow what is written in reliable sources. We can't say "but it shouldn't really be called PAE while in long mode" just because some computer science student (n.b.: I've been teaching this stuff for more than 12 years, so brag to me not about your being a student for that long) thinks that that is "misleading". I have already incorporated a note re. Intel's choice of an alternate terminology. (But because AMD was first, we can't dump their names in preference to Intel's.)

Re. "misleading": You really need to stop using that word. It is undeniable that AMD took the existing PAE structures and "extended" them, adding a fourth level table and supporting more bits of both VA and PA. The PFN field was "extended" from 24 to 40 bits, the supported VA size was "extended" from 32 to 48 bits, and the structures were "extended" from three levels to four. "Extension" refers to making a new version of something by making it larger in some dimension, but following the same basic design. So I don't know what other word than "extensions" to describe the changes that were made to x86 PAE in making x64 PAE... or "ia32e paging", if you insist. In fact, personally I think the result should be called PAEE, or PAE²! (I've used that term often when teaching this stuff, and I find that is not misleading. Instead I find that it helps people understand the relationship between the old and the new schemes. But that's just my invention, so you don't see me trying to put it into the article.)

The fact that this is the only mode available while in long mode is irrelevant to this point: "Extension" is the right word. It's also the word AMD uses.

In short, please stop beating this dead horse. I seriously doubt you will ever get WP:CONSENSUS for the changes you want here. Jeh (talk) 00:13, 9 February 2015 (UTC)

OK, OK, OK, but is there any real processor capable of addressing 52-bit physical space? — Preceding unsigned comment added by 103.25.58.14 (talk) 04:49, 8 February 2015 (UTC)

Good question. Someone will have to go through the various processor product spec sheets to answer it. Note that 2^52 bytes of RAM would require 32,768 DIMMs at DDR4's current max of 128 GiB per DIMM. That would be a big motherboard! :) However, there is value in implementing a larger physical address space than you can have RAM, since the extra bits can be used to mean other things besides memory addresses. For example, this was done on the DEC Alpha platforms to interface PC-style buses to them. Jeh (talk) 00:13, 9 February 2015 (UTC)