Talk:Instruction cycle

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Accuracy

is this even accurate? User_talk:212.219.142.161

Not clear at point 3 ("indirect address" is vague) User_talk:87.5.218.102

True, shouldn't that be direct address, anyway? Olivia Guest 14:18, 23 December 2006 (UTC)[reply]

I think this article should focus on instruction cycles in general (why they're needed, how they operate, and history) rather explain a 5 step cycle. I'm going to fork the specific cycles into separate articles, and clean up this one, if no one objects. falsedef 20:46, 16 January 2007 (UTC)[reply]

Actually, I've found other articles with the correct cycles. I'll clean this page up later. falsedef 23:21, 18 January 2007 (UTC)[reply]

It would be nice if you bring what you've already got here, as other people may start working on the same things.. sorry, just want to avoid a clash.. Coil.uk

This article is clear to me.

the fetch-execute cycle is a load of rubbish —Preceding unsigned comment added by 79.79.6.173 (talk) 22:42, 26 March 2009 (UTC)[reply]

Indeed, there is also a lot of vandalism going on, maybe someone can clean this up and perhaps lock the page? User:Anonymous 11:45, 07 March 2010 (UTC) —Preceding unsigned comment added by 91.105.203.94 (talk) [reply]

Tidy up

I'm not an expert on this topic and it's been a long time since I've studied it at school. As a means of refreshing my knowledge I've decided to read up on the topic with a view to tidying up this page. I've made a few edits already, please review for accuracy. I've tidied up a lot of grammar, I hope I haven't polluted the message. Thanks. --Eamonnca1 (talk) 19:33, 9 July 2010 (UTC)[reply]

Update - I've done a considerable amount of cleaning up here, but that diagram still doesn't tie in with the text on the page. What's the MAR and MDR? Also, I think that step 4 should be 'Interrupt cycle' rather than 'store results' based on that source that I cited later in the article. --Eamonnca1 (talk) 00:08, 10 July 2010 (UTC)[reply]

If the abbreviations MAR, MDR and CIR are to be retained and explained, the diagram needs amending follows: "Load Data Required To MDR" --> "Load Instruction to MDR" and "MAR Contents To CIR" --> "MDR Contents To CIR". AlanS1951 (talk) 11:44, 12 April 2013 (UTC)[reply]

CPUs built in the early years, such as the PDP-8, invariably have a memory address register (MAR), a memory data register (MDR), and an instruction register (IR) that you can physically touch. Because physical registers were so expensive, such early CPUs typically had a total of 5 or fewer physical registers.

Many programmers know nothing about these registers, because that knowledge is not necessary to program the computer, even in assembly language -- they are not part of the programmer-visible instruction set "registers". Those early CPUs pretend to have a dozen or so programmer-visible ISA "registers" by storing most or all of the programmer-visible registers in RAM, only loading one or two of them at a time, when needed by some instruction, into the handful of physical registers. Nowadays, CPUs still pretend to have a dozen or so programmer-visible ISA "registers", even when they have hundreds of physical registers, by using complex register renaming techniques. How can we make this article better? --DavidCary (talk) 03:45, 19 August 2011 (UTC)[reply]

Instruction cycle

Why does it start at 2?? What happened to the all important 1? Anyone? Antonyh3 (talk) 01:58, 9 November 2010 (UTC)[reply]

T-cycle

The Zilog Z80 article mentions "T-cycles". The Intel 8008 article mentions "T-states". Are they really the same thing? Should this instruction cycle explain what those states are? --DavidCary (talk) 03:51, 19 August 2011 (UTC)[reply]

According to their articles, a Z80 t-cycle is one clock cycle and a 8008 t-state is two clock cycles. So no, they're different. They are specific to those machines, and don't belong here. -R. S. Shaw (talk) 06:24, 21 August 2011 (UTC)[reply]

Original Source

I am not a regular wikipedia author and am busy writing at the moment (sorry that I am not just editing the article directly). For my research I tracked down what I believe to be source material for fetch-decode-execute paradigm. It would be nice if someone could include a citation for it:

J. Holland. A universal computer capable of executing an arbitrary number of sub-programs simultaneously. In Papers presented at the December 1-3, 1959, eastern joint IRE-AIEE-ACM computer conference, IRE-AIEE-ACM ’59 (Eastern), pages 108–113, New York, NY, USA, 1959. ACM. — Preceding unsigned comment added by Infinitesteps (talk • contribs) 20:12, 11 November 2012 (UTC)[reply]

Experts

I don't know how to call in an expert from the Wikipedia project Computer Science, but do you think this is a good idea? Halp. — Preceding unsigned comment added by 66.205.158.7 (talk) 19:50, 17 February 2013 (UTC)[reply]

What happens with PC on JUMP instruction?

To my mind, this case should be covered in the article, since it is a special yet very common operation to be performed. Thanks! --2001:638:501:4246:6257:18FF:FEF1:52BB (talk) 19:31, 15 February 2016 (UTC)[reply]

External links modified

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Microcode?

the article doesn't even mention or distinguish microcode? needs serious help. 2604:2000:EED4:A00:0:0:0:2 (talk) 05:33, 1 December 2016 (UTC)[reply]

Flowchart accuracy

In the diagram, the 5th step is "MAR contents to CIR", should this be MDR instead, since the MAR just holds a memory address whilst CIR holds actual instructions? 123.243.171.231 (talk) 04:32, 15 October 2017 (UTC)[reply]

CPU performing steps when each instruction has at most one data fetch and one data write back

In the fetch cycle,

The CPU copies the contents of the PC to MAR prepared for instruction loading.
The memory loads the instruction specified in MAR to MBR/MDR.
The CPU copies the instruction from MBR to IR for instruction decoding.
The CPU increments the PC to point to the next instruction.

In the execute cycle,

To fetch data from memory, CPU generates the address to the MAR and data transfers to the MBR.
IR sends out the appropriate control signals to cause data to be moved from one register to another or an operation to be performed by the ALU taking data from registers.
To write data back to memory, CPU copies the result of the ALU to the MBR. CPU then generates the address and copies to MAR.
The data bus loads the data from MBR to the memory location specified by MAR.

Twnhotel (talk) 06:54, 6 June 2018 (UTC)[reply]