Talk:Clipper architecture

chearing the PSW

What does this mean? Pkunk (talk) 21:20, 28 August 2014 (UTC)

I fixed the typo. Now the article says "clearing the PSW".

I'm guessing that when the Clipper accepts an external interrupt, it acts like it executed the Clipper "calls" instruction ("call supervisor"; "software trap"), which is similar to the interrupt system of many ARM, PIC, AVR, etc. processors.

1. To prevent an interrupt storm from overflowing the stack, when the CPU starts to handle one interrupt, the CPU hardware disables all interrupts from the same or any other source -- the interrupt cannot be interrupted. The Clipper apparently does this by clearing the PSW, which zeros all the interrupt enable bits (also called trap enable bits).
2. The last instruction(s) in the interrupt handler tell the CPU to do the "return from interrupt" process. During that process, the CPU hardware pulls data from the stack; then uses that data to restore the PC, PSW, and SSW to the state they were in before the the CPU was interrupted -- including restoring (some) interrupt enable bits to the "enabled" position.

One reference in this article (the "Clipper 32-Bit Microprocessor Module Instruction Set") describes the details of how the Clipper executes the "calls" instruction. Is there a reference that explicitly states the details of how Clipper handles an interrupt? --DavidCary (talk) 21:26, 11 January 2015 (UTC)

Found it. The CLIPPER C100 Data Sheet explains interrupt handling in detail. And it is indeed exactly like CALLS: PC, SSW and PSW are pushed on the supervisor stack (with the PSW upper byte set to indicate the interrupt or trap source), the PSW is cleared to all-zero, and the new PC and SSW are fetched from the interrupt vector table. (Except for SSW.P, which indicates the previous privilege level.)

71.41.210.146 (talk) 04:38, 14 September 2015 (UTC)