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4 nm demonstration transistor

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An Australian team announced that they fabricated a single functional transistor out of 7 atoms that measure 4nm in length. see [[1]] [[2]] Scalzi+ | (Talk | contribs) 21:51, 24 May 2010 (UTC)[reply]

I think we will get to see all the way down to 1nm and perhaps smaller at around 2030. The reason is because of new technology allowing smaller conductor to work in a new environment. 88.88.19.25 (talk) 16:34, 1 February 2011 (UTC)[reply]
The same team has since improved the process to make a transistor out of a single phosphorous atom. Single-atom transistor is 'perfect' Scalzi+ | (Talk | contribs) 22:45, 19 February 2012 (UTC)[reply]
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During several automated bot runs the following external link was found to be unavailable. Please check if the link is in fact down and fix or remove it in that case!

"SEMICON West - Lithography Challenges and Solutions" re 22 nm - still NF - Rod57 (talk) 10:36, 2 January 2016 (UTC)[reply]
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During several automated bot runs the following external link was found to be unavailable. Please check if the link is in fact down and fix or remove it in that case!

"Intel scientists find wall for Moore's Law" - still NF - now seems to be at Intel scientists find wall for Moore's Law - Will use that.  Done Rod57 (talk) 10:41, 2 January 2016 (UTC)[reply]

Samsung 10nm

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This item does not belong here. It refers to "10 nanometer (nm)-class process technology" This is industry-speak for 1X, ie anything between 10nm and 19nm. It is likely far closer to the latter than the former, so does not belong in an article about the 10nm process. I would just delete it, but I suspect someone will just add it back again, so wanted to note it here first.

156.39.10.21 (talk) —Preceding undated comment added 17:11, 30 April 2013 (UTC)[reply]

Similar items in Technology demos and Mass production. Deleted both as misleading. - Rod57 (talk) 10:54, 2 January 2016 (UTC)[reply]

Not an article as it stands

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The 10 nanometer (10 nm) node is the technology node following the 14 nm node. << That's the first sentence. This page needs to add some context. — Preceding unsigned comment added by 91.123.162.38 (talk) 22:22, 17 May 2013 (UTC)[reply]

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comparison section is garbage - discussion - revision

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Do not re-add that comparison table and that entire section without discussing it here first because the section I deleted was just nonsense. It was clearly written by people who had no clue what they are talking about.

Problems with that section:

  • The ITRS no longer exists
  • The ITRS NEVER sets "Ground Rules" EVER. They made a roadmap for the industry BASED ON HOW THE INDUSTRY BEHAVED and create roadmaps based on educated guesses. That means they were often wrong and they self-adjust according as new nodes ramped up. In fact, adjustments were always made after 2 leading nodes ramped up
  • Some values in the table were guessed and un-sourecd
  • THere is NO SUCH THING AS A 1/3 "rule of thumb" like who the hell seriously wrote that - the reference to that crap is "http://www.eenewseurope.com/news/samsung%E2%80%99s-14-nm-lpe-finfet-transistors/page/0/3" which was the AUTHOR'S OWN ATTEMPT to normalize the node names. It's just his own thing (and btw, it's not even correct).
    • "Intel does not satisfy this rule of thumb at around 11 nm," 1) that's someones own personal research and 2) same crap as I pointed out above, no such damn rule 3) it's exactly why the author's own nonsense were incorrect
  • "and Intel, Samsung, and TSMC's 10 nm process nodes do not meet all of the International Technology Roadmap for Semiconductors (ITRS) logic device ground rules for this process node." Other than being personal research, note that it's clear whomever wrote it has no clue what they are talking about. If we checked whether the industry node "meets all the ITRS reqs" then NO NODES WOULD. That's because the ITRS ADJUSTS itself after new process nodes come out. Historically speaking the ITRS roadmaps were considerably off (sometimes by an order of magnitude actually). Unfortunately the ITRS no longer exists and therefor the roadmap hasn't been updated.
  • "However, as Samsung's 10 nm process is better than Intel's 14 nm process," seriously, who wrote that garbage? First of all, that's not even Wikipedia:NPOV, secondly looking at the IEDM papers the opposite appears to be true (at least as far as drive current is concerned), but thirdly and most importantly, YOU CANNOT MAKE THOSE ASSESSMENTS WITHOUT ACTUALLY EVALUATING THE Process design kit (PDK)!!! A bunch of transistor attributes is insufficient.


Discuss here before adding anything from that section back. --CyberXRef☎ 06:09, 12 May 2017 (UTC)[reply]

I removed a similar section from the 14 nanometer article. Looks like someone literally copy and pasted the same crap there as well. --CyberXRef☎ 06:12, 12 May 2017 (UTC)[reply]

The itrs exists, actually read the corresponding document to see logic device ground rules, will take out unsourced values, rule of thumb thing probably won't mention as it is arbitrary. Again, look at the document and compare to see that they do not meet the logic device ground rules. Some nodes do, and some don't meet these rules, not looking for perfect accuracy but rather to just use it as a third party comparison as a way to move forward measuring process transistor density. Samsung's 10 nm process is better than Intel's 14 nm process discussing strictly density, which is what these articles are for, not electrical properties like performance at different drive currents, which are not discussed here and are a whole different topic entirely then. — Preceding unsigned comment added by 199.119.233.244 (talk) 02:59, 13 May 2017 (UTC)[reply]

It might also be better to be constructive on wikipedia rather than destructive. If you don't like something, change it, don't just delete it. — Preceding unsigned comment added by 199.119.233.244 (talk) 03:18, 13 May 2017 (UTC)[reply]

Disclaimer: I used to be on that working group a long while ago so I can shed some light on your inaccuracies. (note that I don't work for any of those companies so I'm neutral from that respect)
I will delete everything that makes no sense. False and misleading information is worse than no information; we had many of them.
  • The ITRS no longer exists. Last roadmap is in fact the LAST roadmap.
  • The ITRS has been replaced by a similar working group called the "International Roadmap for Devices and Systems" (or IRDS). It's similar but different mission goals.
  • "actually read the corresponding document to see logic device ground rules" - You seem to have a misunderstanding of what the ITRS is and what their role is. The documents the ITRS publishes are white papers detailing the existing semiconductor processes and a roadmap of where they think the future direction of the industry is. They do not lay out ground rules for the industry and they don't set requirements. They simply make predictions; predictions that often turned out to be incorrect it should be noted. They also detail the various breakthroughs in research and development that has taken place at various companies (read: primarily Intel and IBM, now it's mostly Intel).
  • The roadmap is exactly that, a roadmap. And as I stated before, the roadmap gets re-adjusted once 2 leading processes ramp up their production.
  • The reason the roadmap is re-adjusted is because it's almost never right the first time and there are always unexpected things.
    • Stating a process doesn't fit the roadmap is highly misleading because historically (ever since 0.25-micron really) that has been the case. Lg out-paced the roadmap. When this was "corrected" the roadmap failed to accuracity predict a stall in the gate length at ~30nm (in fact a stall in planar transistor characteristics as a whole was not predicted for 30nm).
    • "Again, look at the document and compare to see that they do not meet the logic device ground rules" once again, this is simply wrong.
This is what the 2012 roadmap looked like:
Year2011201220132014201520162017201820192020202120222023202420252026
M1 Half Pitch38nm32nm27nm24nm21nm18.9nm16.9nm15nm13.4nm11.9nm10.6nm9.5nm8.4nm7.5nm7.5nm7.5nm
This is what the reality is (Average between leading edge):
Year2011201220132014201520162017201820192020202120222023202420252026
M1 Half Pitch~56nm~50nm~45nm~30nm~30nm~30nm~23nm~23nm~19nm~19nm
Wo! everything on the roadmap is off, who would've guessed? Do we say the 32nm node "does not fit the ground rules"? absolutely not! We update the ITRS roadmap to fit the industry!
Let's check what the ITRS roadmap looked like for 2013!
Year201120122013201420152016201720182019202020212022202320242025202620272028
M1 Half Pitch40nm31.8nm31.8nm28.3nm25.3nm22.5nm20.0nm17.9nm17.9nm15.9nm14.2nm12.6nm11.3nm10.0nm8.9nm8nm
Look at that! we're looking much better now, aren't we? We're still off for the later nodes because of the switch to FinFET.
  • "Again, look at the document and compare to see that they do not meet the logic device ground rules. Some nodes do, and some don't meet these rules" Historically speaking the roadmap was off close to 100% of the time. As far as 0.5 µm in ~1993 timeframe.
  • "rule of thumb" is not only arbitrary is JUST NONSENSE
    • Once we left the legacy planar transistor node names are just that, names. Trying to make up some 1/3 nonsense to "make the node name fit" is HIGHLY misleading to the average reader that had no real understanding of what a transistor is, let alone a process node.
  • Samsung's 10 nm process is better than Intel's 14 nm process discussing strictly density, which is what these articles are for, not electrical properties like performance at different drive currents, which are not discussed here and are a whole different topic entirely then.
  • First of all, this article is about a "10 nanometer node". We're talking about the entire transistor and not about one single variable (density) you selected for some reason.
  • Secondly, "Better" doesn't mean "strictly density". NEVER did. It's because we have things like dark silicon to deal with. "Better" is a combination of ideal threshold voltage, high drive current, low leakage current, tight control, and yes density.
  • Thirdly, even if you wanted to go by density (and btw it's mostly original research at this point), we only have their proposed HD SRAM bitcell to go by and Samsung's 10nm is "0.040 µm²" vs Intel's "0.0499 µm²". And note that Samsung's numbers are off from their actual production number. ChipWorks/TechInsight measured their 10nm transistors from the Snapdragon 835 in their galaxy phone at "68nm x 51nm" which is not exactly the numbers they announced "64nm x 48nm" (see this). Whereas Intels "70 nm x 52 nm" are indeed measured as such. So even that statement is incorrect. Doesn't look like it's actually denser, it's more or less the same.
  • Fourthly as I stated in my previous comment, the only way to tell which one is "better" (With respect to the properties I noted above) is to delve into the PDK and not only would this be entirely original research, it would be nearly impossible considering you'd be signed off on an NDA.


You can see why I have great objections in adding information that is severely misleading to the reader. --CyberXRef☎ 18:10, 13 May 2017 (UTC)[reply]
I've not deleted everything, but I have trimmed it down to the actual points without any of the wikipedia:original research and wikipedia:opinion portions. --CyberXRef☎ 18:34, 13 May 2017 (UTC)[reply]

The ITRS and other organizations change their roadmaps periodically. The ITRS has not officially shut down; it still has a website and presence on social media networks. I understand the logistics behind these semiconductor roadmaps. Currently, the IRDS has the same "Logic Device Ground Rules" as the ITRS as it appears they've copied and pasted the same page. I would not put too much energy worrying specifically about these numbers, as if changed, you can update these "ground rules" as they are released. The way I've stated that device nodes either fail or pass ITRS specifications may be too strict, so I'll try to change that. I only meant to use these logic device rules as a third party to compare against. For the purpose of this article, I don't care about what they are or even what the industry does; they are just something to compare against. They are called "Logic Device Ground Rules" because that is what they are actually named in the document, although it is true that they are more like guidelines. Yes, gate lengths used to be the way that the industry measured process nodes and that has stalled.

In this article, we are not generally talking about entire transistor specifications, but usually more strictly about density in relation to semiconductors. I did change the wording to address strictly density. Samsung's 10 nm documentation and Intel's 14 nm documentation compared will show you that Samsung has greater density. You can perhaps make Wikipedia articles on Samsung's 10 nm process node or Intel's 14 nm process node if you would like to go into detail on them.

You claim no foundry relations, yet your actions exhibit a possible Intel affiliation. Your past comments indicate a clear defense primarily against statements not necessairily favorable to Intel. You also deleted the 14 nm article part on Intel using only the latest process node at the base layer, but didn't say anything about that. This cheats the customer and is true information and properly sourced as well. Nobody had a problem with these pages until you came along. Do you by any chance work out of Intel's Israeli office where they work on manufacturing more advanced process nodes, as your User Page shows that you identify yourself as Jewish? I know that Intel has this little narrative to play that they're 3 years in advance of everybody (which is perhaps why you deleted the table so that these numbers can't be compared easily), but this is an uncertain and subjective assessment of the situation, considering much of this is speculation as Samsung may have better density and TSMC has just recently started mass producing their 10 nm process which has even greater density supposedly. I see that Samsung might also not be wholeheartedly be telling the truth about their process node, but a tweet from a guy named Dick James on Twitter is not a good, verifiable source on Wikipedia unless he has an article published on the subject. The Tech Insights article illustrates the 68 nm pitch, but not the 51 nm number. If you can find a proper, reliable source with both of these numbers verified, then these dimensions can be added. Currently, only the 68 nm one can.

I see what you did in the article, and although it helps to shorten things, there's no table and thus no visualization and it can be hard for certain people to read and compare these numbers, especially those with certain disabilities, which is why a table was designed for this purpose. You also identify yourself as Dyslexic, so deleting the table doesn't make any sense for a Dyslexic person as reading the numbers would be more difficult, unless they have ulterior motives such as a possible affiliation with Intel. If you find a proper, verifiable source, then if you want you can also add that Intel's 14 nm offers better performance or efficiency than Samsung's 10 nm if this is found to be true. — Preceding unsigned comment added by 199.119.233.189 (talk) 02:45, 14 May 2017 (UTC)[reply]

After all that, I'm glad that we have the 'comparision' table. It gives some context to the "10nm" label. - Rod57 (talk) 10:37, 10 June 2018 (UTC)[reply]

Comparison table - process names, density

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A useful table - but can we be more specific about the foundries process names - some of them have/evolve multiple processes at each 'node' ?
Also what metric should we use for 'density'? - [3] uses "Gate Pitch (GP) multiplied by Metal 1 Pitch (M1P)" - Rod57 (talk) 12:44, 10 June 2018 (UTC)[reply]

Intel 14nm++ is said to be "higher performance" than Intel's initial 10nm process - For comparison we could include a column for Intel 14nm++ ? - Rod57 (talk) 14:30, 10 June 2018 (UTC)[reply]

Why are the 14nm rules and Intel 14nm specs in this table? What's the point of that? — Preceding unsigned comment added by YouBloodyMook (talk • contribs) 22:32, 7 September 2018 (UTC)[reply]

For comparison. The 10nm processes of TSMC and Samsung are closer to the 16/14nm ITRS rules and to Intel's 14nm process. — Pizzahut2 (talk) 23:02, 7 September 2018 (UTC)[reply]

Can IBM CNT be used for logic circuits

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Under Technology demos and pre-production it says "In 2012, IBM produced a sub-10 nm carbon nanotube transistor that outperformed silicon on speed and power.[16] "The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies", according to the abstract of the paper in Nano Letters.[17]"
I don't have access to the source but could someone clarify if this could be used for integrated logic chips eg for CPUs/GPUs ? For CMOS I think we need enhancement mode NMOS and PMOS transistors ? Sounds like they only hand-made one working transistor - was it enhancement mode or depletion mode ? Abstract just says "... we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade—nearly half of the value expected from a previous theoretical study." - Earlier (2002) IBM work on CNTs is described in tunnel field-effect transistor (TFET) but makes it sound unlikely for mainstream applications. Implies other materials might be used for complementary? TFET logic for beyond-CMOS. - Rod57 (talk) 14:52, 10 June 2018 (UTC)[reply]

Pat Gelsinger quote

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Can we please keep the Pat Gelsinger quote? It's a great quote and I've been waiting since 2008 for those 10 nm chips. — Preceding unsigned comment added by 64.64.95.88 (talk) 04:34, 19 October 2018 (UTC)[reply]

Just what is pitch, anyway?

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A helpful graphic describing just what the heck all these dimensions are referring to would be useful. Someone knowledgeable please sketch a "typical" transistor on a "typical" chip, and label the various dimensions. Something along the lines of: "A 10nm-class chip typically has transistors that occupy an area of 40nm x 40nm (I just pulled the number out of thin air) the 10nm-class has a smallest feature size of 10nm, meaning (this little bump here) is typically approximately 11.189547567 nm across." --73.83.14.130 (talk) 19:24, 22 October 2018 (UTC)[reply]

How are nodes chosen, defined, and described?

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Where's a link to this information? How do we compare Samsung's 10nm process to Intel's? Is a node just a performance spec, (10 gigaflops using less than 50W, it doesn't matter how small the transistors are) or does it describe a specific size (Transistors occupy 10nmx10nm area, and the chip could perform 1 flop and use 100000W?). --73.83.14.130 (talk) 19:24, 22 October 2018 (UTC)[reply]

This doesn't really explain how the nodes are chosen, but this interview Gamers Nexus did with David Kanter is a good primer on the difference between the "foundry" 10nm and Intel 10nm nodes: https://www.youtube.com/watch?v=dtiBEHH7mEA . In any case, I'd generally concur with Wikichip's page "Technology Node", which states that "The number itself has lost the exact meaning it once held. Recent technology nodes [...] refer purely to a specific generation of chips." Generally, foundaries just develop a new smaller, more efficient node, and then choose which class they think it fits in, based on some VERY loose guidelines from the ITRS roadmap (which has now been discontinued, apparently?) Sorry I couldn't be more specific, but it's all just a very fuzzy area ATMarsdenTalk 20:39, 24 October 2018 (UTC)[reply]
I actually just found the 2017 IRDS (successor to the ITRS) roadmap - it outlines "expected" measurements at each successive node from "10" (Intel 10/Foundry 7) down through 7, 6, 3, 2.1, 1.5, and 1.0 nm (Intel 1.0/Foundry 0.7) nodes. A lot of the actual dimensions don't scale much beyond i5-f3, but these are the "expected" values for these nodes, which is generally roughly where the foundries try to aim their production. The use of different transistor types (finFET at 20/16/14/12/10, lateral gate-all-around at 7/5/3/2.1/1.5/1.0, and vertical gate-all-around at 3/2.1/1.5/1.0/0.7) accounts for improved performance even where the actual transistor size is unchanged, although again, this is mostly just academic as the fabs can decide what they want to call *THEIR* node anyway. Personally, I think Intel should just skip a number soon to make them just as "wrong" as the foundry numbering. ATMarsdenTalk 20:49, 24 October 2018 (UTC)[reply]

Wikichip

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Is Wikichip a high enough quality source to be used in citations? I feel it isn't but would like to know other people's opinions as itt is used to back up some contentious assertions in this article. 87.75.117.183 (talk) 19:40, 23 August 2019 (UTC)[reply]

As much as it sucks to cite a wiki, I have to acknowledge that these people are seriously dedicated to writing about the chip stuff and crunching datasheets and stuff. The WikiChip Fuse service is not a wiki but a normal news site, so it's technically okay as a source. --Artoria2e5 🌉 09:48, 4 August 2020 (UTC)[reply]

Comparing GlobalFoundries 7nm and Intel 10nm might be irrelevant.

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GlobalFoundries never shipped 7nm products and has shifted to producing older process nodes. This comparison would still make sense between TSMC or Samsung however, as their 7 and 8nm nodes are approximately the same density as Intel 10nm.

The comparison is correct, just perhaps not very useful seeing as the products never materialized from GlobalFoundries. They do exist from Samsung and TSMC, so that might be a more relevant comparison. Benny121221 (talk) 00:47, 31 March 2021 (UTC)[reply]

"8 nanometer" listed at Redirects for discussion

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A discussion is taking place to address the redirect 8 nanometer. The discussion will occur at Wikipedia:Redirects for discussion/Log/2021 August 31#8 nanometer until a consensus is reached, and readers of this page are welcome to contribute to the discussion. Gaioa (T C L) 13:17, 31 August 2021 (UTC)[reply]

Intel 7

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There is a content dispute over whether Intel 7 should be described as a 10 nm or 7 nm process, or described in some other way. See Talk:7 nm process § Intel 7 for the ongoing discussion. — Newslinger talk 09:35, 28 September 2023 (UTC)[reply]

i'd say 10esf is a 7 nanometer process based off of this: https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros and all others are 10nmPancho507 (talk) 09:53, 9 November 2023 (UTC)[reply]
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