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Draft:Keshab K. Parhi

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Keshab K. Parhi
Born1959 (1959)
Bhadrak District, Odisha, India
CitizenshipUnited States
Awards
Academic background
Alma mater
ThesisAlgorithm and Architecture Design for High-Speed Signal Processing (1988)
Doctoral advisorDavid G. Messerschmitt
Academic work
InstitutionsUniversity of Minnesota, Twin Cities (UMN)
Doctoral studentshttps://www.genealogy.math.ndsu.nodak.edu/id.php?id=41741
Main interestsVLSI, Signal Processing, Artifical Intelligence, Neural Engineering, DNA Computing
Websitehttps://www.ece.umn.edu/users/parhi/

Keshab K. Parhi (born 1959 (1959) in Bhadrak District, Odisha, India) is an electrical engineer and computer scientist. He is currently the Erwin A. Kelen Chair in the department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. His research addresses architecture design of VLSI integrated circuit chips for signal processing, communications, artificial intelligence, and cryptosystems with a focus on reducing latency and increasing speed, while also reducing chip area and energy consumption. His research has also addressed neural engineering and DNA computing.[1]

Career

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Parhi received the B. Tech. degree from the Indian Institute of Technology, Kharagpur in 1982, the M.S. degree from the University of Pennsylvania in 1984, and the Ph.D. degree from the University of California, Berkeley in 1988. He joined the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities in October 1988. He was promoted to Associate Professor with tenure in July 1992 and promoted to full professor in July 1995. From July 1997 to June 2022, he held the Edgar F. Johnson Professorship in Electronic Communication. Since July 2022, he holds the Erwin A. Kelen Chair in Electrical Engineering. From July 2008 to August 2011, he served as the Director of Graduate Studies of the Electrical Engineering Program.[1]

Parhi has been a Visiting Professor at the Delft University of Technology (1996), Lund University (1999), Fudan University (2017), and Stanford University (2018). He has held short-term appointments at IBM T.J. Watson Research Center (1986), Bell Laboratories (1987), NEC C&C Laboratory (1992 and 1996-1997 on a US National Science Foundation-Cooperative Government Program (CGP) Fellowship),[2] Broadcom Corporation (2000-2002), and Medtronic (2006-2007). From 2005 to 2012, he served as Founder, President, and Chief Scientist of Leanics Corporation. Leanics was supported by SBIR funding from the National Science Foundation and the Department of Defense.[1]

Research

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Parhi’s interdisciplinary research in late 1980s advanced the field of VLSI signal processing by integrating concepts from computer architecture, digital signal processing (DSP), and VLSI design. In particular, he developed algorithm transformations techniques[3] such as unfolding[4] and folding[5] for DSP programs described by iterative data-flow graphs.

His research has led to pipelined-parallel architectures for signal processing operations such as recursive[6][7] and adaptive[8][9] digital filters, decision-feedback equalizers,[10][11] Tomlinson-Harashima precoders,[12][13] parallel decision-feedback decoders,[14] and fast Fourier transforms.[15][16][17] He has developed architectures for modern error correction encoders/decoders including turbo codes,[18] low-density parity-check codes,[19][20] and polar codes.[21][22] His research has been deployed in numerous integrated circuit chips for physical-layer communications in wired and wireless media that form the backbone of the internet.

His research has led to high-speed architectures for cryptosystems such as the advanced encryption standard (AES),[23] post-quantum cryptography,[24] and homomorphic encryption.[25] He has also developed approaches to obfuscating integrated circuits using keys to prevent the sale of excess parts and to protect key parameters of the design.[26][27] In the 1990s, Parhi worked on a DARPA funded project on high-level synthesis that led to the development of the Minnesota Architecture Synthesis System (MARS) for time-constrained and resource-constrained synthesis of data-flow graphs.[28] His research group also developed the Hierarchical Energy Analysis Tool (HEAT) to estimate power consumption with circuit-simulation-level accuracy from logic-level simulation.[29]

Literary Works

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  • Keshab K. Parhi (1999). VLSI Digital Signal Processing Systems: Design and Implementation. Wiley-Interscience. ISBN 978-0-471-24186-7.
  • Shanbhag, N.R.; Keshab K. Parhi (1994). Pipelined Adaptive Digital Filters (The Springer International Series in Engineering and Computer Science, 274). Springer. ISBN 978-1-4613-6151-0.
  • Hartley, R.; Keshab K. Parhi (1995). Digit-Serial Computation (The Springer International Series in Engineering and Computer Science, 316). Springer. ISBN 978-1-4613-5985-2.
  • Chung, J.-G.; Keshab K. Parhi (1996). Pipelined Lattice and Wave Digital Recursive Filters (The Springer International Series in Engineering and Computer Science, 344). Springer. ISBN 978-1-4612-8560-1.
  • Keshab K. Parhi; Nishitani, T. (1999). Digital Signal Processing for Multimedia Systems (Signal Processing and Communications). CRC Press. ISBN 9780824719241.

Parhi has also authored over 725 papers and is inventor or co-inventor of 36 issued US patents.[30]

Professional Service

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Parhi has served the Institute of Electrical and Electronics Engineers (IEEE) in various capacities. He has served as Associate Editor for numerous transactions published by the IEEE Circuits and Systems Society and the IEEE Signal Processing Society. His leadership roles include:[1]

Distinctions and Awards

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  • 2017 – IEEE Circuits and Systems Society Mac Van Valkenburg Award for pioneering contributions to VLSI digital signal processing architectures, design methodologies, and their applications to wired and wireless communications, and service to IEEE Circuits and Systems Society[37]
  • 2012 – IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award for contributions to VLSI architectures and design methodologies for digital signal processing and communications circuits and systems.[40]
  • 2003 – IEEE Kiyo Tomiyasu Award for pioneering contributions to high-speed and low-power digital signal processing architectures for broadband communications systems[42]
  • 1996 – Fellow, IEEE for contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools[44]

References

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  1. ^ a b c d e f g "Keshab K. Parhi Homepage". www.ece.umn.edu. Retrieved 26 December 2024.
  2. ^ "NSF-CGP Fellowship: VLSI Digital Signal Processing and Multimedia Systems". www.nsf.gov. Retrieved 26 December 2024.
  3. ^ Parhi, K.K. (December 1989). "Algorithm Transformation Techniques for Concurrent Processors". Proceedings of the IEEE. 77 (12): 1879–1895. doi:10.1109/5.48830.
  4. ^ Parhi, K.K.; Messerschmitt, D.G. (February 1991). "Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding". IEEE Transactions on Computers. 40 (2): 178–195. doi:10.1109/12.73588.
  5. ^ Parhi, K.K.; Wang, C.-Y.; Brown, A.P. (January 1992). "Synthesis of Control Circuits in Folded Pipelined DSP Architectures". IEEE Journal of Solid-State Circuits. 27 (1): 29–43. Bibcode:1992IJSSC..27...29P. doi:10.1109/4.109555.
  6. ^ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in Recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1099–1117. doi:10.1109/29.32286.
  7. ^ Parhi, K.K.; Messerschmitt, D.G. (July 1989). "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering". IEEE Transactions on Acoustics, Speech, and Signal Processing. 37 (7): 1118–1134. doi:10.1109/29.32287.
  8. ^ Parhi, K.K.; Messerschmitt, D.G. (October 1987). "Concurrent Cellular VLSI Adaptive Filter Architectures". IEEE Transactions on Circuits and Systems. 34 (10): 1141–1151. doi:10.1109/TCS.1987.1086048.
  9. ^ Shanbhag, N.R.; Parhi, K.K. (December 1993). "Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder". IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing. 40 (12): 753–766. doi:10.1109/82.260240.
  10. ^ Parhi, K.K. (July 1991). "Pipelining in Algorithms with Quantizer Loops". IEEE Transactions on Circuits and Systems. 38 (7): 745–754. doi:10.1109/31.135746.
  11. ^ Parhi, K.K. (April 2005). "Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers". IEEE Transactions on VLSI Systems. 13 (4): 489–493. doi:10.1109/TVLSI.2004.842935.
  12. ^ Gu, Y.; Parhi, K.K. (September 2007). "High-Speed Architecture Design of Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems, Part I: Regular Papers. 54 (9): 1929–1937. doi:10.1109/TCSI.2007.904688.
  13. ^ Gu, Y.; Parhi, K.K. (May 2008). "Design of Parallel Tomlinson-Harashima Precoders". IEEE Transactions on Circuits and Systems, Part II: Express Briefs. 55 (5): 447–451. doi:10.1109/TCSII.2007.914435.
  14. ^ Gu, Y.; Parhi, K.K. (February 2007). "Pipelined Parallel Decision Feedback Decoders for High-Speed Ethernet over Copper". IEEE Transactions on Signal Processing. 55 (2): 707–715. Bibcode:2007ITSP...55..707G. doi:10.1109/TSP.2006.885776.
  15. ^ Cheng, C.; Parhi, K.K. (October 2007). "High-Throughput VLSI Architecture for FFT Computation". IEEE Transactions on Circuits and Systems II: Express Briefs. 54 (10): 863–867. doi:10.1109/TCSII.2007.901635.
  16. ^ Ayinala, M.; Brown, M.J.; Parhi, K.K. (June 2012). "Pipelined Parallel FFT Architectures via Folding Transformation". IEEE Transactions on VLSI Systems. 20 (6): 1068–1081. doi:10.1109/TVLSI.2011.2147338.
  17. ^ Parhi, K.K. (April 2024). A Low-Latency FFT-IFFT Cascade Architecture. Proc. of 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). pp. 181–185. doi:10.1109/ICASSP48485.2024.10447370.
  18. ^ Wang, Z.; Chi, Z.; Parhi, K.K. (December 2002). "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders". IEEE Transactions on VLSI Systems. 10 (12): 902–912. doi:10.1109/TVLSI.2002.808451.
  19. ^ Zhang, T.; Parhi, K.K. (April 2004). "Joint (3,k)-regular LDPC Code and Decoder/Encoder Design". IEEE Transactions on Signal Processing. 52 (4): 1065–1079. Bibcode:2004ITSP...52.1065Z. doi:10.1109/TSP.2004.823508.
  20. ^ Chen, Y.; Parhi, K.K. (June 2004). "Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check Codes". IEEE Transactions on Circuits and Systems I: Regular Papers. 51 (6): 1106–1113. doi:10.1109/TCSI.2004.826194.
  21. ^ Yuan, B.; Parhi, K.K. (April 2014). "Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding". IEEE Transactions on Circuits and Systems I: Regular Papers. 61 (4): 1241–1254. doi:10.1109/TCSI.2013.2283779.
  22. ^ Yuan, B.; Parhi, K.K. (December 15, 2014). "Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders". IEEE Transactions on Circuits and Systems I: Regular Papers. 62 (24): 6496–6506. Bibcode:2014ITSP...62.6496Y. doi:10.1109/TSP.2014.2366712.
  23. ^ Zhang, X.; Parhi, K.K. (September 2004). "High-Speed VLSI Architectures for the AES Algorithm". IEEE Transactions on VLSI Systems. 12 (9): 957–967. doi:10.1109/TVLSI.2004.832943.
  24. ^ Tan, W.; Wang, A.; Zhang, X.; Lao, Y.; Parhi, K.K. (September 2023). "High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography". IEEE Transactions on Computers. 72 (9): 2454–2466. arXiv:2110.12127. doi:10.1109/TC.2023.3251847.
  25. ^ Tan, W.; Chiu, S.-W.; Wang, A.; Lao, Y.; Parhi, K.K. (January 2024). "PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption". IEEE Transactions on Information Forensics and Security. 19: 1646–1659. arXiv:2303.02237. doi:10.1109/TIFS.2023.3338553.
  26. ^ Lao, Y.; Parhi, K.K. (May 2015). "Obfuscating DSP Circuits via High-Level Transformations". IEEE Transactions on VLSI Systems. 23 (5): 819–830. doi:10.1109/TVLSI.2014.2323976.
  27. ^ Koteshwara, S.; Kim, C.H.; Parhi, K.K. (January 2018). "Key-Based Dynamic Functional Obfuscation of Integrated Circuits using Sequentially-Triggered Mode-Based Design". IEEE Transactions on Information Forensics and Security. 13 (1): 79–93. doi:10.1109/TIFS.2017.2738600.
  28. ^ Wang, C.-Y.; Parhi, K.K. (March 1995). "High-Level DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation". IEEE Transactions on Computer Aided Design. 14 (3): 274–295. doi:10.1109/43.365120.
  29. ^ Satyanarayana, J.; Parhi, K.K. (June 1996). HEAT: Hierarchical Energy Analysis Tool. ACM/IEEE Design Automation Conference. pp. 9–14. doi:10.1109/DAC.1996.545536.
  30. ^ "Keshab K. Parhi - Google Scholar". scholar.google.com. Retrieved 30 December 2024.
  31. ^ "Charles E. Bowers Faculty Teaching Award, UMN CSE". cse.umn.edu. Retrieved 26 December 2024.
  32. ^ "Dr. Keshab Parhi Elected to the 2022 Class of the AIMBE College of Fellows" (PDF). aimbe.org. Retrieved 26 December 2024.
  33. ^ "IEEE Circuits and Systems Society John Choma Education Award Recipients". ieee-cas.org. Retrieved 26 December 2024.
  34. ^ "2020 ACM Fellows Recognized for Work that Underpins Today's Computing Innovations". www.acm.org. Retrieved 26 December 2024.
  35. ^ "U of M Professor Keshab Parhi to be inducted into the National Academy of Inventors". twin-cities.umn.edu. Retrieved 26 December 2024.
  36. ^ "2017 AAAS Fellows Recognized for Advancing Science". www.aaas.org. Retrieved 26 December 2024.
  37. ^ "IEEE Circuits and Systems Society Mac Van Valkenburg Award Recipients". ieee-cas.org. Retrieved 26 December 2024.
  38. ^ "Distinguished Alumni Awards List". www.iitkgpfoundation.org. Retrieved 26 December 2024.
  39. ^ "Keshab Parhi - Scholars Walk". scholarswalk.umn.edu. Retrieved 30 December 2024.
  40. ^ "IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award Recipients". ieee-cas.org. Retrieved 26 December 2024.
  41. ^ "Division Awards Archive, Electrical and Computer Engineering Division". monolith.asee.orgorg. Retrieved 26 December 2024.
  42. ^ "IEEE Kiyo Tomiyasu Award". ethw.org. Retrieved 30 December 2024.
  43. ^ "IEEE W.R.G. Baker Award". ethw.org. Retrieved 30 December 2024.
  44. ^ "IEEE Fellows Directory". services27.ieee.org. Retrieved 26 December 2024.
  45. ^ "NYI: Dedicated VLSI Digital Signal and Image Processors". www.nsf.gov. Retrieved 26 December 2024.
  46. ^ "IEEE Browder J. Thompson Memorial Prize Paper Award". ethw.org. Retrieved 26 December 2024.
  47. ^ "IEEE Signal Processing Society Young Author Best Paper Award" (PDF). signalprocessingsociety.org. Retrieved 26 December 2024.
  48. ^ "Eli Jury Award". www2.eecs.berkeley.edu. Retrieved 26 December 2024.
  49. ^ "Demetri Angelakos Memorial Achievement Award". www2.eecs.berkeley.edu. Retrieved 26 December 2024.
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