Jump to content

Draft:HILO HDL

From Wikipedia, the free encyclopedia

HILO [1][2][3]was one of the first commercial Hardware Description Languages used to describe and simulate electronics circuits.

It had one language for electronic hardware description, and a different language for stimulus and simulator control.

The HDL was completely declarative, consisting of a hierarchical netlist of sub-units, primitive gates, and flip-flops, as well as configurable functions.

The HILO project started in the UK in early 1970s (HILO-1)[4] and was commercialized at Brunel University in the 1980s (HILO-2[5][6]) and later by Cirrus Computers and finally by GenRad (HILO-3[7]).

HILO-1 was purely structural and HILO-2 added the first Register Transfer Language (RTL) with timing.

HILO-1 was written in assembler, HILO-2 was written in the BCPL language.

The HILO-2 project at Brunel had Peter Flake as the Technical Authority and Phil Moorby, Simon Davidmann, and others, working on the language and simulators.

HILO-2 had two simulators - a fault-free logic simulator for exploring a designs behavior, and a fault simulator for simulating a design with faults injected to grade tests for functional board testing.

In 1981 Prabhu Goel of Wang Labs. Mass., USA, became the first USA customer of HILO-2 to be used in the design and verification of a 10,000 gate ASIC.

In 1982 Prabhu left Wang and set up what became Gateway and subsequently hired Phil Moorby who evolved the HILO-2 structural description syntax and keywords into Verilog with minor changes.

In 1984 HILO-2 was acquired by GenRad and the HDL was renamed GHDL (GenRad HDL) with the simulator being called HILO-3 and being re-written in C and ported to Unix.

Ultimately Verilog became the HDL and simulator of choice in the industry and interest in HILO reduced.





References

[edit]
  1. ^ Newton, Richard (2005). "Presentation of the 2005 Phil Kaufman Award to Phil Moorby".
  2. ^ Dettmer, R. (2004). "The HILO inheritance". IEE Review. 50 (8): 22–26. doi:10.1049/ir:20040803.
  3. ^ Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proc. ACM Program. Lang. 4 (HOPL): 87:1–87:90. doi:10.1145/3386337.
  4. ^ Flake, P.L. (1975). "A digital Systems Simulator - HILO". Digital Processes. 1: 39–53.
  5. ^ Davidmann, Simon (1981). "HILO-2 team members".
  6. ^ Harris, R. L.; Davidmann, S. J.; Musgrave, G. (1984-01-01), Wexler, Joanna (ed.), "HILO-2 - A SYSTEM TO BUILD ON", CAD84, Butterworth-Heinemann, pp. 48–60, ISBN 978-0-408-01440-3, retrieved 2025-01-04
  7. ^ Wharton, David (1983). "Introduction to the HILO-3 Logic Simulator" (PDF).