Draft:Design and Verification Tools Integrated Development Environment
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Submission declined on 8 October 2024 by Sir MemeGod (talk).
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| Submission declined on 4 October 2024 by S0091 (talk). This draft's references do not show that the subject qualifies for a Wikipedia article. In summary, the draft needs multiple published sources that are:
This submission appears to read more like an advertisement than an entry in an encyclopedia. Encyclopedia articles need to be written from a neutral point of view, and should refer to a range of independent, reliable, published sources, not just to materials produced by the creator of the subject being discussed. This is important so that the article can meet Wikipedia's verifiability policy and the notability of the subject can be established. If you still feel that this subject is worthy of inclusion in Wikipedia, please rewrite your submission to comply with these policies. Declined by S0091 31 days ago. | |
Comment: I still don't see notability, a lot of the sources (specifically the Eclipse News one) seem to be primary, and "SemiWiki" appears to be a wiki. :) SirMemeGod 16:31, 8 October 2024 (UTC)
- Comment: Sources are primary, not independent and/or not reliable (user-generated content such as wikis or blogs). S0091 (talk) 17:21, 4 October 2024 (UTC)
Design and Verification Tools Integrated Development Environment (DVT IDE) is a commercial integrated development environment developed by AMIQ EDA released in 2008,[1] designed for hardware design and verification engineers working with hardware description and verification languages.
Features
[edit]DVT IDE includes several features intended to support engineers in hardware design and verification tasks:
- Multi-Language and Mixed-Language Support: Support for multiple languages including SystemVerilog, Verilog, VHDL,[2] and e language.[3][4]
- Intelligent Refactoring: Context-aware renaming of symbols through code compilation and resolving identifiers and references.[2]
- Design Hierarchy and Structural Browsing: Visual representation of modules, interfaces, and components within the design.[2]
- Support for UVM, OVM, VMM: Integration for the Universal Verification Methodology (UVM), Open Verification Methodology (OVM) and Verification Methodology Manual (VMM),[5] with features such as UVM compliance checking, UVM-simulation log recognition,[6] and UVM factory queries, templates, browsers, and sequence trees for testbench development.[2]
- Simulator Integration: Integration with major simulators like NCSim, Specman, VCS, and Questa for in-project simulation and debugging via the DVT Debugger add-on,[2] with support for real-time syntax and semantic checks, automatic testbench compatibility verification, and initial port mapping.[7]
- Macro Expansion and Programming: Analysis and debugging of macros within the codebase through macro expansion and programming capabilities.[2]
- Testbench Linting: Auditing and compliance features for adherence to coding guidelines and verification methodologies through the Verissimo SystemVerilog Testbench Linter add-on.[7]
Licensing
[edit]DVT IDE operates under a commercial licensing model, utilizing a per-language licensing approach where users must purchase separate licenses for each hardware description or verification language. Add-ons such as DVT Debugger and Verissimo require additional licenses.[2]
References
[edit]- ^ Dawson, S.; Ballance, M. (February 2019). Introducing your team to an IDE (PDF). Design & Verification Conference & Exhibition. Retrieved 8 October 2024.
- ^ a b c d e f g Daniyal Khurram, Syed; Chan, Horace (October 2018). IDEs Should Be Available to Hardware Engineers Too! (PDF). Design & Verification Conference & Exhibition. Retrieved 3 October 2024.
- ^ Goering, Richard (10 April 2006). "VERIFICATION: IEEE standardizes 'e' language". EDN. AspenCore, Inc. Retrieved 3 October 2024.
- ^ Linehan, Éamonn; O'Toole, Eamonn; Clarke, Siobhán (5 July 2012). "Model-driven automation for simulation-based functional verification" (PDF). ACM Trans. Des. Autom. Electron. Syst. 17 (3): 31:16. doi:10.1145/2209291.2209304.
- ^ Cohen, Ben; Venkataramanan, Srinivasan; Kumari, Ajeetha; Piper, Lisa (15 October 2015). SystemVerilog Assertions Handbook (PDF) (4th ed.). self-published. pp. xix, xxiii–xxiv. ISBN 978-1518681448. Retrieved 7 October 2024.
- ^ Rosenberg, Sharon; Rosenberg, Sharon (2010). A practical guide to adopting the Universal Verification Methodology (UVM). San Jose, Calif: Cadence Design Systems. p. 145. ISBN 978-0-578-05955-6. Retrieved 7 October 2024.
- ^ a b Zdraveski, Vladimir; Dimitrovski, Andrej; Trajanov, Dimitar (April 2014). HDL IP Cores System as an Online Testbench Provider. 5th Small Systems Simulation Symposium. Retrieved 3 October 2024.
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