Draft:Crestmont (microarchitecture)
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Crestmont is the codename for Intel's fifth generation out of order Atom microarchitecture, and is the successor to Gracemont. It is used as the efficient-core and low power efficient-core microarchitecture in Intel's first generation Core Ultra processors (codenamed "Meteor Lake")[1], and Xeon 6 E-core processors (codenamed "Sierra Forest")[2].
| General information | |
|---|---|
| Launched | November 4, 2023[3] |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 0.4 GHz to 3.8 GHz |
| Cache | |
| L1 cache | 96 KB per core:
|
| L2 cache | 2 or 4 MB per module |
| L3 cache | 3 MB per module (not present in Crestmont LP)[4] |
| Architecture and classification | |
| Instruction set | x86-64 |
| Extensions | |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code names |
|
| History | |
| Predecessor | Gracemont |
| Successor | Skymont |
Design
[edit]Crestmont contains the following enhancements over Gracemont:[5]
- 6 wide rename and dispatch, compared to 5-wide in Gracemont
- 6144 entry L2 Branch Target Buffer, compared to 5120 in Gracemont
- Branch predictor can scan 128 bytes per cycle, compared to 32 bytes per cycle in Gracemont
- Renamer can eliminate more µops by itself
- Floating point divide latency reduced to 5 cycles, from 10 in Gracemont
- Floating point scheduler sizes increased to a total of 60 entries, from 55 in Gracemont
- L2 TLB size increased to 3072 entries with 6-way associativity, from 2048 entries with 4-way associativity
Technology
[edit]- Manufactured on Intel 4 (Meteor Lake compute tile)[1], Intel 3 (Sierra Forest compute tile)[6], or TSMC N6 (Meteor Lake SoC tile)[1]
- 2 three-wide decoders in a cluster, each capable of fetching 32 bytes per cycle from the instruction cache
- 6-wide rename/dispatch[7]
- 256 entry reorder buffer[8]
- 17 execution ports with distributed schedulers[5]
- 32 kilobyte L1 data cache with eight-way associativity and 3 cycle latency[5]
- 64 kilobyte L1 instruction cache with eight-way associativity[8]
- 2-4 megabyte L2 cache with sixteen-way associativity and 17 cycles of latency shared between up to four cores[8]
- Access to shared L3 cache with P-cores or other E-core modules on Meteor Lake and Sierra Forest
List of Crestmont processors
[edit]See also
[edit]References
[edit]- ^ a b c Alcorn, Paul (September 20, 2023). "Intel Details Core Ultra 'Meteor Lake' Architecture, Launches December 14". Tom's Hardware. Archived from the original on June 8, 2024. Retrieved June 27, 2024.
- ^ Larabel, Michael (June 3, 2024). "Intel Launches Xeon 6700E "Sierra Forest" CPUs - Initially Up To 144 Cores". Phoronix. Archived from the original on June 4, 2024. Retrieved June 27, 2024.
- ^ Smith, Ryan (September 19, 2023). "The Intel Innovation 2023 Live Blog". AnandTech. Retrieved June 10, 2024.
- ^ Smith, Ryan (September 19, 2023). "The Intel Innovation 2023 Live Blog". AnandTech. Retrieved June 27, 2024.
- ^ a b c Lam, Chester (June 10, 2024). "Meteor Lake's E-Cores: Crestmont Makes Incremental Progress". Chips and Cheese. Archived from the original on May 28, 2024. Retrieved June 10, 2024.
- ^ Conway, Adam (26 September 2023). "Intel's process roadmap to 2025: Intel 7, 4, 3, 20A, and 18A explained". XDA-Developers. Archived from the original on March 28, 2024. Retrieved March 26, 2024.
- ^ "Meteor Lake's E-Cores: Crestmont Makes Incremental Progress". Chips and Cheese. 13 May 2024. Archived from the original on May 28, 2024. Retrieved June 10, 2024.
- ^ a b c Smith, Ryan (August 28, 2023). "Hot Chips 2023: Intel Details More on Granite Rapids and Sierra Forest Xeons". Anandtech. Archived from the original on May 11, 2024. Retrieved June 27, 2024.
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