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Dynamic approaches to reduce power in digital circuits

Adaptive Voltage Scaling (AVS) is a closed-loop dynamic power minimization technique which reduces power based on the actual operating conditions of the chip. As an example, the power consumption can be continuously adjusted during the run time of the chip. Typically, chip design ensures that the chip meets the most demanding application requirements under worst case operating conditions, which means that the chip, under typical operating conditions, wastes power. AVS is beneficial compared to conventional dynamic voltage scaling (DVS) because AVS eliminates the excess power margins that are present in the DVS systems due to the fixed voltage-frequency relations employed in those systems. Under AVS the chip's exact process corner is determined during manufacturing or runtime and the appropriate Voltage-Frequency relationship is determined, which will be used during the dynamic voltage and frequency scaling operations. This eliminates the extra margin that was present because worst case operating conditions were taken into account during the chip's construction.

Background

Technology advancements have enabled very powerful and versatile computing systems to be designed on smaller chips. As smaller chip size allows for more functions to be implemented in the same area, there is an escalation in current density and the associated power dissipation. As the demands for higher processing power and faster clock-rates increase, the power consumption and thermal performance of integrated circuits emerge as the limiting factor for high-performance processor systems. Also the need for reducing the self-heating of the processor chips operating in automotive temperature environments enhances the need for solutions that reduce power dissipation. A lot of techniques can be used to transform a high-performance system into a low power system. However, minimizing power consumption in digital CMOS circuits requires a lot of design effort at system, architectural, circuit and device levels. Supply Voltage reduction technique is one of the most effective ways of reducing the power consumption. Nevertheless, one direct consequence of static supply voltage scaling is performance degradation. To maintain the desired throughput, dynamic voltage scaling systems are used to adjust the supply voltage according to the throughput requirements. But there is still a large amount of power margin wasted in the open-loop DVS systems and to overcome this AVS systems are being examined.

Overview

Adaptive voltage scaling is a closed-loop dynamic voltage scaling approach that considers process variations from device to device on a chip, temperature fluctuations during the chip operations and load variations,and then establishes a voltage-frequency relation for the reduction in power dissipation of the circuit under that condition. The features offered by this approach are

• Delivery of desired Accurate voltage to every block of the system even across the temperature, process corner and frequency variations.
• Processor and architecture independent implementation of power reduction .
• Typical savings of about 55% over the Open-loop Dynamic voltage scaling Approaches.

The adaptive voltage scaling technique is specifically used to address the energy saving requirements of application-specific integrated circuits, microprocessors or systems on chips. However, the AVS approach is ideally suited for high-volume systems such as data centers and wireless base stations, as well as for the power constrained applications such as portable devices, USB peripherals, or consumer electronics.

Comparison between dynamic and adaptive voltage scaling

The architecture of generic Dynamic Voltage Scaling system has a performance manager, a phase-locked loop and a voltage regulator. The performance manager block uses a software interface in order to predict the performance requirements of the next task. Once the determination of the power requirement is done, the voltage and frequency are set by the performance manager in order to finish the task. The phase-locked loop accomplishes the frequency scaling depending on the target frequency set by the performance manager. Similarly the voltage regulator is programmed to scale the supply voltage so as to achieve the target voltage for the task. Thus, the characterization of the systems employing DVS requires characterization at at least two ends of operating range. In fact, the characterization of DVS systems depends on the underlying voltage scaling methodology. The basic operation of both open-loop DVS systems (the conventional DVS systems) and the closed loop DVS systems (Adaptive voltage systems) is same with the difference lying in the selection of the target voltage-frequency relationship. The open-loop DVS systems employ the one-to-one mapping of the voltage to frequency to perform the voltage scaling. The frequency-voltage pairs are stored in lookup table and are obtained as per the determined task needs. In case of the open-loop DVS systems the frequency-voltage relationship is determined by considering the chip characterization at worst case conditions so as to guarantee the robust operation under the temperature and process variations. Thus in order to accommodate for the worst case variations there is a lot of power margin left by the open-loop DVS systems for power scaling. This margin is not lost in closed loop systems because they employ a feedback mechanism that keeps probing the actual on chip conditions and according to that the target voltage and frequency are determined. The most important design parameters are to be considered while choosing between the Open-loop and closed loop configurations is stability against temperature fluctuations. The temperature stability is guaranteed in the conventional open-loop systems because they are chosen for worst case conditions. But the energy savings are drastically reduced due to the large margins considered.

Implementation of circuit that monitors on-chip-variations in the AVS systems

The closed loop voltage scaling system utilizes on chip circuit structures to provide feedback required to adaptively track the actual silicon behavior. One most commonly used approach is to use a ring oscillator that operates at the same voltage as that of the rest of the chip. The voltage-frequency relationship for the chip at that particular frequency is determined by the frequency of the ring oscillator.

Critical path monitoring techniques

Critical Path Monitoring Technique for Adaptive Voltage Scaling

The voltage-frequency relationship for the chip can also be determined by using another approach in which a critical path monitor tries to model the critical path of the chip. The critical path of the system can be duplicated using a ring oscillator or by a fanout of four ring oscillator or a delay line. This critical path replica (delay line) provides the closest behavior to the actual critical path except for the intra-die variations and cross coupling capacitances which are hard to duplicate. This delay line adapts to environmental and process variations. As the actual performance of the core and the speed of the delay line are directly related, a closed-loop adaptive voltage scaling system is obtained to automatically adjust the supply voltage such that the minimum needed voltage is supplied so as to perform the target task.The delay chain consists of inverters, NAND gates, wire segments, etc, and the output can be tapped from one of the points, thus allowing tuning of the delay to match chips critical path. A reconfigurable delay chain can also be used in a critical path monitoring technique. It is during the manufacturing test, the exact setting of the delay chain is determined. During the AVS operation, in order to measure the delay launch an edge at the start of the clock cycle and then capture the edge at the end of the clock cycle at the output of delay chain and a set of buffers. Then the buffer outputs that are captured are analyzed to determine the exact positioning of the rising edge. Now the feedback employed by the AVS system continually adjusts the supply voltage such that the delay chain and critical path meet the timing constraints with adequate margins. The adjustment of supply voltage is done such that the launched rising edge makes it to a specified buffer stage which ensures the timing of delay line.

Challenges in Critical Path Monitoring Techniques

Sufficient safety margins are to be included in order to account for any mismatch between the delay line(critical path monitor) and the actual critical path in order to account for the large within-die process variations that are inevitable.These large variations can cause the critical path to change from one process corner to other.Thus in order to maintain a fail safe operation, an additional delay margin is to be maintained.This margin is translated into voltage overhead that directly reduces the energy savings associated with the AVS approach. The process and temperature variations of the closed loop systems are compensated by continuously monitoring the activity of critical path replica. Nevertheless, in the sub-micrometer technologies the use of a single reference in the critical path is becoming less feasible. As the transistor dimensions are scaled, selection of a unique critical path across all conditions becomes very challenging. This is because of the increased variations of transistor and wires with the progress of technology node. Also when the contribution of interconnect delay increases, there might be several paths that have different combinations of logic and interconnect delay with their overall delays being close to each other. In that case the selection of critical path becomes even more challenging.

Razor Approach

In order to overcome the bottlenecks of the Critical path approach implementation of AVS system, the Razor approach is used. Unlike the critical path approach where a single path is identified as critical path, the Razor approach has a set of potential paths that are to be monitored. In this approach an on-chip timing checker is employed to check the timing margin of the set of critical path. A delayed version of the system clock is used by the timing circuit to capture the data in shadow latch which is same as the data captured by the master (main) flip-flop. Wherever the sub paths become critical, additional shadow latches are introduced. When the supply voltage is scaled the value latched in the main flip-flop might be different from that of those latched by the shadow latches, which results in an error signals. The error signals from all the shadow latches are gathered to generate a single error indicator. This error is corrected by flushing the pipeline and reloading the state that was existing before the error occurred. When the error rates decrease beyond certain limits the supply voltage is reduced till the point where the error tends to become unacceptable.

Challenges in Razor approach

• In order to guarantee the robust operation the system characterization at all conditions is to be known which requires an increased number of latches. This increases the error probability as well as the overhead of error detection circuit.
• When the error rate increases, the latency which arises due to flushing of the pipeline might negatively affects the overall system performance.
• When the design has many critical paths which are close to each other in timing, then more shadow latches are needed resulting in increased overhead and reduced efficiency. This increases the complexity of razor approach.

Issues related to Bias Temperature Instability

Bias temperature instability, an aging [sic?] mechanism in CMOS technology causes time dependent degradation in VLSI circuits. Adaptive voltage scaling can be used to mitigate the BTI-induced timing degradation by increasing the supply voltage dynamically. This can be achieved as long as the BTI degradation is captured by performance sensor in the AVS system. However the use of AVS during the lifetime of the chip poses new challenges for the margin reduction in the sign-off methodology which characterizes the timing libraries based on the transistor models with the pre-calculated BTI degradation for given integrated circuit life time.

See also

• Power Dissipation
• Low Power Electronics
• Dynamic Voltage scaling
• Bias Temperature Instability

References

Category:Electricity