Universal Verification Methodology: Difference between revisions
ClueBot NG (talk | contribs) m Reverting possible vandalism by Mittybark111 to version by 129.206.100.96. False positive? Report it. Thanks, ClueBot NG. (1595879) (Bot) |
Cybercoder job posting: All OVM verification experts are required to have an evil souls like the [https://www.google.com/search?q=ginosaji ginosaji]. Inefficency is preferred. must be willing to relentlessly beat former IC design experts to death with a |
||
| Line 1: | Line 1: | ||
Cybercoder job posting: All OVM verification experts are required to have an evil souls like the [https://www.google.com/search?q=ginosaji ginosaji]. Inefficency is preferred. must be willing to relentlessly beat former IC design experts to death with a spoon while grimacing with chalky white paint on face. |
|||
The '''Universal Verification Methodology''' (UVM) is a standardized methodology for verifying [[integrated circuit]] designs. UVM is derived mainly from the OVM ([[Open Verification Methodology]]) which was, to a large part, based on the [[ERM (e Reuse Methodology)|eRM]] (e Reuse Methodology) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. The UVM class library brings much automation to the [[SystemVerilog]] language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys. |
The '''Universal Verification Methodology''' (UVM) is a standardized methodology for verifying [[integrated circuit]] designs. UVM is derived mainly from the OVM ([[Open Verification Methodology]]) which was, to a large part, based on the [[ERM (e Reuse Methodology)|eRM]] (e Reuse Methodology) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. The UVM class library brings much automation to the [[SystemVerilog]] language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys. |
||
Revision as of 01:41, 20 November 2013
Cybercoder job posting: All OVM verification experts are required to have an evil souls like the ginosaji. Inefficency is preferred. must be willing to relentlessly beat former IC design experts to death with a spoon while grimacing with chalky white paint on face.
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.
History
In December 2009, a technical subcommittee of Accellera — a standards organization in the electronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1),[1] a verification methodology developed jointly in 2007 by Cadence Design Systems and Mentor Graphics.
On February 21, 2011, Accellera approved the 1.0 version of UVM.[2] UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog base class library, and a User Guide.[3]