IBM System/370-XA

System/370-XA

Designer	IBM
Bits	32-bit
Introduced	1983 (1983)
Design	CISC
Type	Register–Register Register–Memory Memory–Memory
Encoding	Variable (2, 4 or 6 bytes long)
Branching	Condition code, indexing, counting
Endianness	Big
Predecessor	System/370
Successor	ESA/370
Registers
General-purpose	16
Floating point	4 64-bit

IBM S/370-XA registers

General Registers 0-15 Two's complement value 0 31

Control Registers 0-15 See Principles of Operation 0 31

Floating Point Registers 0-6 S Biased exponent Mantissa 0 1 7 8 31 Mantissa (continued) 32 63

Extended Architecture Extended Control mode PSW 0 R 0 0 0 T I O E X Key 1 M W P S 0 CC Program Mask 0 0 0 0 0 0 0 0 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31 A Instruction Address 32 33 63 S/370-XA EC mode PSW abbreviations Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O Mask; subject to channel mask in CR2 7 EX External Mask; subject to external subclass mask in CR0 8-11 Key PSW key 12 E=1 Extended Control mode 13 M Machine-check mask 14 W Wait state 15 P Problem state 16 S Address-Space Control 0=primary-space mode 1=Secondary-space mode 18-19 CC Condition Code 20-23 PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance 32 A Addressing mode 0=24 bit; 1=31 bit 33-63 IA Instruction Address IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

IBM System/370-XA is an instruction set architecture introduced by IBM in 1983 for the IBM 308X processors. It extends the IBM System/370 architecture to support 31-bit virtual and physical addresses, and includes a redesigned I/O architecture.

31-bit virtual addressing

In the System/360, other than the 360/67, and System/370 architectures, the general-purpose registers were 32 bits wide, the machine did 32-bit arithmetic operations, and addresses were always stored in 32-bit words, so the architecture was considered 32-bit, but the machines ignored the top 8 bits of the address resulting in 24-bit addressing. Much of System/360's and System/370's large installed code base relied on a 24-bit logical address; In particular, a heavily used machine instruction, LA, Load Address, explicitly cleared the top eight bits of the address being placed in a register. If the 24-bit limit were to be removed, this would create migration problems for existing software.

This was addressed by adding an addressing mode bit to the Program Status Word controlling whether the program runs in 24-bit mode, in which the top eight bits of virtual addresses are ignored, or 31-bit mode, in which only the uppermost bit of virtual addresses are ignored. Several reasons were given for the choice of 31 bits instead of 32 bits:

1. The desire to retain the high-order bit as a "control or escape bit." In particular, the standard subroutine calling convention marked the final parameter word by setting its high bit.
2. Interaction between 32-bit addresses and two loop control instructions, BXH and BXLE that treated their arguments as signed numbers when doing comparisons (and which was said to be the reason TSS used 31-bit addressing on the Model 67).
3. Input from key initial Model 67 sites, which had debated the alternatives during the initial system design period, and had recommended 31 bits (instead of the 32-bit design that was ultimately chosen at the time).

Certain machine instructions in this 31-bit addressing mode alter the addressing mode bit. For example, the original subroutine call instructions BAL, Branch and Link, and its register-register equivalent, BALR, Branch and Link Register, store certain status information, the instruction length code, the condition code and the program mask, in the top byte of the return address. A BAS, Branch and Save, instruction was added to allow 31-bit return addresses. BAS, and its register-register equivalent, BASR, Branch and Save Register, was part of the instruction set of the 360/67, which was the only System/360 model to allow addresses longer than 24 bits. These instructions were maintained, but were modified and extended for 31-bit addressing.

Additional instructions in support of allowing calls between 24-bit-addressing and 31-bit-addressing code include two new register-register call/return instructions which also effect an addressing mode change, BASSM, Branch and Save and Set Mode, the 24/31 bit version of a call where the linkage address including the mode is saved and a branch is taken to an address in a possibly different mode, and BSM, Branch and Set Mode, the 24/31 bit version of a return, where the return is directly to the previously saved linkage address and in its previous mode. Taken together, BASSM and BSM allow 24-bit calls to 31-bit (and return to 24-bit), 31-bit calls to 24-bit (and return to 31-bit), 24-bit calls to 24-bit (and return to 24-bit) and 31-bit calls to 31-bit (and return to 31-bit).

Like BALR 14,15 (the 24-bit-only form of a call), BASSM is used as BASSM 14,15, where the linkage address and mode are saved in register 14, and a branch is taken to the subroutine address and mode specified in register 15. Somewhat similarly to BCR 15,14 (the 24-bit-only form of an unconditional return), BSM is used as BSM 0,14, where 0 indicates that the current mode is not saved (the program is leaving the subroutine, anyway), and a return to the caller at the address and mode specified in register 14 is to be taken.

31-bit physical addressing

System/370 initially supported only 24-bit physical addresses; the extended real address feature extended this to 26-bit addresses.

System/370-XA changed the page table entry format to support 19 bits of page frame address; pages are 4 KB in 370-XA, so combining a 19-bit page frame address with a 12-bit offset within the page produces a 31-bit physical address. Channel command words can be in one of two formats, with format 0 being the System/370 format, with a 24-bit data address, and format 1 being an additional format, with a 31-bit data address.

I/O

System/370-XA introduced a channel subsystem that performed I/O queuing previously done by the operating system.