Open Verification Methodology: Difference between revisions
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OVM is just a shitty way to connect verification blocks together |
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The '''Open Verification Methodology''' (OVM) is a documented [[methodology]] with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008<ref>[http://www.ovmworld.org/press_release_010908.php OVM 1.0 Announcement]</ref>, and regular updates have expanded its functionality. The latest version is OVM 2.1.1, released in April, 2010. The current release and all previous releases are available, under the [[Apache License]], on the OVM World<ref>[http://www.ovmworld.org OVM World]</ref> site. |
The '''Open Verification Methodology''' (OVM) is a documented [[methodology]] with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008<ref>[http://www.ovmworld.org/press_release_010908.php OVM 1.0 Announcement]</ref>, and regular updates have expanded its functionality. The latest version is OVM 2.1.1, released in April, 2010. The current release and all previous releases are available, under the [[Apache License]], on the OVM World<ref>[http://www.ovmworld.org OVM World]</ref> site. |
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==OVM is NOT an advanced testbench environment== |
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I'm sick of hearing stupid people making false claims that only OVM is an advanced testbench environment. OVM is just a shitty way to connect verification blocks together by using methods that are only available in a standard programming language such as c++ or e. There's nothing advanced about it. People have been writing '''advanced testenches''' for years. Long before the OVM marketing people copied and renamed the standard testbench components and then claimed they invented everything. I was writing scoreboards, monitors, checkers, drivers, randomizers, bfms wayback in the 90's, long before OVM, eVM, UVM, etc... OVM is no more reusable or easy to maintain then the previous methods. The language constructs that really make reuse possible are the addition of SystemVerilog Features like queues and associative arrays, structures, etc. |
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==Misc== |
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The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology) which was, to a large part, based on the [[ERM (e Reuse Methodology)|eRM]] (e Reuse Methodology) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. The OVM also brings in concepts from the AVM (Advanced Verification Methodology (AVM). The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc. The UVM also has recommendations for code packaging and naming conventions. |
The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology) which was, to a large part, based on the [[ERM (e Reuse Methodology)|eRM]] (e Reuse Methodology) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. The OVM also brings in concepts from the AVM (Advanced Verification Methodology (AVM). The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc. The UVM also has recommendations for code packaging and naming conventions. |
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Revision as of 03:25, 7 September 2011
The Open Verification Methodology (OVM) is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008[1], and regular updates have expanded its functionality. The latest version is OVM 2.1.1, released in April, 2010. The current release and all previous releases are available, under the Apache License, on the OVM World[2] site.
OVM is NOT an advanced testbench environment
I'm sick of hearing stupid people making false claims that only OVM is an advanced testbench environment. OVM is just a shitty way to connect verification blocks together by using methods that are only available in a standard programming language such as c++ or e. There's nothing advanced about it. People have been writing advanced testenches for years. Long before the OVM marketing people copied and renamed the standard testbench components and then claimed they invented everything. I was writing scoreboards, monitors, checkers, drivers, randomizers, bfms wayback in the 90's, long before OVM, eVM, UVM, etc... OVM is no more reusable or easy to maintain then the previous methods. The language constructs that really make reuse possible are the addition of SystemVerilog Features like queues and associative arrays, structures, etc.
Misc
The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The OVM also brings in concepts from the AVM (Advanced Verification Methodology (AVM). The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc. The UVM also has recommendations for code packaging and naming conventions.
The OVM has won recognition from Electronic Design Magazine[3] and a DesignVision award from the International Engineering Consortium[4].
The OVM was co-developed by Mentor Graphics and Cadence Design Systems, and they continue to guide its evolution in concert with the nine user companies of the OVM Advisory Group[5]. The OVM is publicly supported by more than 60 partner companies[6] offering tools, training, and services.
The OVM was standardized within Accellera, which voted to make it the basis for the Universal Verification Methodology (UVM)[7]. Accellera released version UVM 1.0 EA on May 17, 2010 [8]..